Responsibilities

1. Be responsible for block RTL code development and integration for system control unit. Focus on RISC-V ( or ARM CPU) IP integration and related sub-system blocks’coding.
2. Work with architect team (SOC/IP) to define block feature
3. Work with SOC DV team to define the test plan
4. Work with implementation team to close the timing
5. Integrate block design into SOC
6. Support silicon bringup

Qualifications

1. Be familiar with ASIC design flow and RTL coding, be able to do optimization for area, performance and power
2. Be familiar with system boot, power control and thermal control
3. Be familiar with asynchronous design
4. Be familiar with SOC architecture, has experience in the protocol such as AXI, AHB or APB
5. Be familiar with the external communication interface such as I2C, SPI, PCIe are plus
6. Be familiar with the data transaction control such as DMA is a plus
7. Self-motivated, proactive, team work and achievement oriented
8. Good communication skill and work well with cross-functional teams and technical leadership are big plus